1. Field of the Invention
The invention relates generally to semiconductor integrated circuit devices having gate arrays and, more particularly, it relates to layouts of semiconductor integrated circuit devices having less clock skews and noises.
2. Description of the Background Art
With recent advancement of industrial use of a semiconductor integrated circuit device, the needs for each user have been diversified. The life cycle of a product has also been shortened. For that reason, there is an increasing need for designing a circuit free of defect in a short period of time for product development, and then manufacturing the product with less cost of development. Integration of a semiconductor integrated circuit device has also made remarkable advances. While the number of devices included in one chip has been greatly increased, it is becoming very difficult to make up a circuit utilizing them in accordance with the needs for each user. This conflicts with the need of the above-mentioned shorter period of time for development and the reduction in the cost of development.
In order to meet these needs, a semiconductor integrated circuit device including a gate array has been adopted. A gate array is an integrated circuit device including an array of basic cells arranged regularly on a semiconductor substrate. A basic cell is an assembly of devices required for constituting some function. A desired logic circuit may be obtained by combining basic cells into one unit. A gate array is an integrated circuit device which includes an arrangement of basic cells, in which an interconnection for connecting the basic cells has not been formed yet.
FIG. 1 is a typical diagram of a gate array semiconductor integrated circuit device. Referring to FIG. 1, the chip 26 of this semiconductor integrated circuit device includes basic cell columns 28 provided near the center of the surface, having basic cells arranged regularly, an interconnection region 29 provided around the basic cell columns 28, in which later an interconnection is formed for connecting the basic cells to the basic cells and to an input-output buffer which will be described later, an input-output buffer region 27 provided around the interconnection region 29, in which are formed transistors and the like required for forming a circuit for effecting input and output between the basic cell columns and an external circuit, and a pad forming region 35 around the input-output buffer region 27, in which are formed connecting pads 30 for connecting this semiconductor chip 26 with the external circuit, a power supply pad 61 to which an external power supply is connected, and a ground pad 62 to which a ground potential is connected.
Referring to FIGS. 2, 4, and 5, a basic cell 48 included in the basic cell column 28 includes, for example, p channel MOS (Metal-Oxide Semiconductor) transistors 82, 83 formed on an n-type silicon semiconductor substrate 71, and two n channel transistors 84, 85 formed on a P-type well 72 formed on the main surface of the silicon substrate 71.
Referring to FIG. 4, the p channel transistor 82 includes two p.sup.+ diffusion regions 73, 74 formed on the surface of the semiconductor substrate 71 with a prescribed spacing therebetween, a gate oxide film formed on the main surface of the semiconductor substrate 71 between the p.sup.+ diffusion regions 73, 74, and a polysilicon layer 79 formed on the gate oxide film.
The pMOS 83 includes a p.sup.+ diffusion layer 74, a p.sup.+ diffusion layer 75 formed, spaced apart from the p.sup.+ diffusion layer 74, a gate oxide film formed on the main surface of the semiconductor substrate 71 between the p.sup.+ diffusion layers 74, 75, and a polysilicon layer 80 formed on the gate oxide film.
Referring to FIG. 5, the nMOS 84 includes n.sup.+ diffusion layers 76, 77 formed on a p-type well 72 and spaced from each other between a gate oxide film formed on the surface of the p-type well 72 between the n.sup.+ diffusion layers 76, 77, and a polysilicon layer 79 formed on the gate oxide film.
The nMOS 85 includes an n.sup.+ diffusion layer 77, an n.sup.+ diffusion layer 78 formed on the p-type well 72, and spaced apart from the n.sup.+ diffusion layer 77, a gate oxide film formed on the surface of the p-type well 72 between the n.sup.+ diffusion layers 77, 78, and a polysilicon layer 80 formed on the gate oxide film.
A silicon oxide film 81 is formed on the pMOSs 82, 83, and the nMOSs 84, 85. The polysilicon layer 79 of the pMOS transistor 82 and the polysilicon layer 79 of the nMOS transistor 84 are common, forming a gate electrode of each transistor. Similarly, the polysilicon layer 80 of the pMOS transistor 83 and the polysilicon layer 80 of the nMOS transistor 85 are common, forming a gate electrode of each transistor.
The gate array semiconductor integrated circuit device includes a multiplicity of basic cells 48 (FIG. 2) as stated above, arranged regularly in the basic cell columns 28. A transistor group, as stated above, used as an input-output buffer is also formed in advance in the input-output buffer region 27. There is no interconnection for connecting each of these transistors. That is, it can be said that the gate array chip 26 shown in FIG. 1 is an incomplete semiconductor integrated circuit device.
FIG. 6 is a typical diagram showing the process in manufacturing a semiconductor integrated circuit device for each user with use of a gate array chip. Referring to FIG. 6, at first, a process called master design is conducted in which a layout of the gate array chip as shown in FIG. 1 is designed. As a result of the master design, a master mask 87 is obtained. A master slicer 86 is obtained by diffusing impurities on the semiconductor substrate with use of the master mask 87, and forming a polysilicon layer. A plurality of gate array chips as shown in FIG. 1 are formed on the master slicer 86. The manufactured master slicers 86 are stocked.
In manufacturing a new semiconductor integrated circuit device in accordance with a demand of a user, firstly, a circuit which agrees with the users need is designed. Basic circuits, for example, different kinds of logic gates and flipflops are designed in advance, using basic cells, and the result is registered in a library. In accordance with a circuit design for each user, an interconnection for implementing the circuit required by the user on the master slicer 86 is automatically calculated and determined by a computer. This is called an automatic layout interconnection. As a result of the automatic layout interconnection, personalized masks 88, 89 are formed in which an interconnection pattern to be added to the master slicer 86 is only recorded in order to implement an integrated circuit for each user. This process is called a "personalization". The personalized masks 88, 89 accordingly differ in accordance with the need of the customer.
An interconnection is formed on the master slicer 86 with metal and so on in accordance with the personalized masks 88, 89. The semiconductor integrated circuit on which an interconnection is formed is assembled with peripheral circuits, subjected to a final test, and forwarded to the user.
That is, a semiconductor integrated circuit device with use of a gate array may be obtained by stocking a master slicers having a specific arrangement of basic cells as a semi-finished product, and processing it in accordance with the need of each user. Accordingly, a gate array has advantages below.
Firstly, less cost is required for developing a final product. It takes less than in the case in which a specific design is conducted from the beginning for each user because a master slicer common to all the users is used. The time period required for developing a final product is shorter because it is required only to determine what kind of interconnection should be formed on the master slicer. It is possible to effect an automatic layout interconnection by the computer to the gate array with use of a library as stated above, therefore allowing the semiconductor integrated circuit device with a gate array to be developed without error and in a short period of time. Additionally, for example, in developing a large scale computer, it is necessary to make a large number of chips including a multiplicity of gates. In this case, a gate array is suitable because it can be manufactured at a low cost, and a debugging is readily conducted.
As stated above, a gate array is becoming very important in developing a semiconductor integrated circuit device. With improvement in integration of an integrated circuit, however, the number of flipflops or latches included in a gate array is increased. It is also necessary to meet the need that the device should be operated at a high speed. For that, it is necessary to make a skew as small as possible which occurs in a clock signal provided to a flipflop included in each basic cell. A skew is a deviation of the timing of a clock signal supplied to each flipflop.
Consider the case in which pulses 90a, 90b of a clock signal supplied to flipflops at two different points do not deviate from each other in time as shown in FIGS. 7 (a) and (b). The time period T1 is long enough for the cycle time for operating the system. However, as shown in FIGS. 8 (a), (b), considering the case in which a large skew occurs to the pulses 90a, 90b of the clock signal supplied to different flipflops, the cycle time should be made longer, such as T2. Otherwise, the state of each flipflop included in the semiconductor integrated circuit device becomes disordered. That is, when there is a skew, an operating speed of a semiconductor integrated circuit device is not increased. Even if integration of the semiconductor integrated circuit device is increased, its operating speed remains the same.
Accordingly, there has been proposed a method in which a skew is controlled by distributing the clock signal to a plurality of drivers. FIG. 9 is a plan view of a chip 26 of a gate array semiconductor integrated circuit device in which such a method is adopted. Referring to FIG. 9, the chip 26, as well as the gate array semiconductor integrated circuit device shown in FIG. 1, includes basic cell columns 28, an interconnection region 29 provided around the basic cell columns 28, an input-output region 27 provided around the interconnection region 29, and a pad forming region around the input-output region 27, along the outer periphery of the chip 26.
In a part of the input-output buffer region 27, there is provided a clock signal driver 33 connected to one clock input pad 32 formed in the pad forming region 35 for providing a clock signal to the basic cell columns 28 with a sufficient drive capability. In each basic cell column 28 are formed one or a plurality of subdrivers 31 for distributing and providing a clock signal supplied through a clock signal interconnection 34 from the clock signal driver 33, to flipflops in each basic cell column 28 through a clock signal interconnection 36.
In the pad forming region 35, there are formed, in addition to the clock signal input pad 32, signal bonding pads 30 arranged regularly, a pad 61 for power supply to which an external power supply provided to the chip 26 is connected, and a grounding pad 62 to which a circuit in the chip 26 is connected. The pad forming region 35 adjoining the pad for power supply 61, and the input-output buffer region form a power supply pin region 63. Part of the pad forming region 35 adjoining the grounding pad 62 and part of the input-output region 27 form a ground pin region 64.
FIG. 10 is an enlarged plan view of a region 65 including the power supply pin region 63 and the ground pin region 64 shown in FIG. 9. Referring to FIG. 10, in the input-output buffer region, there are formed a power supply interconnection 37 for output buffer connected to the pad 61 for providing the power supply to the output buffer, a ground interconnection 38 for output buffer connected to the grounding pad 62 for connecting each output buffer with an external ground potential, a power supply interconnection 39 for providing the power supply to an input buffer and a prebuffer, and a ground interconnection 40 for connecting the input buffer and the prebuffer with an external ground potential.
In a lower portion of the power supply interconnection 37 for output buffer in the input-output buffer region 27 except the region of the power supply pin region 63 and the ground pin region 64, pMOS transistors 41 for output buffer are formed. Similarly, in the lower portion of the ground interconnection 38 for output buffer, nMOS transistors 42 for output buffer are formed. In the lower portion of the power supply interconnection 39 for input buffer and prebuffer, pMOS transistors 43 for input buffer and prebuffer are formed. In the lower portion of the ground interconnection 40 for input buffer and prebuffer, nMOS transistors 44 for input buffer and prebuffer are formed. The source of the pMOS transistor 41 is connected to the interconnection 37. The source of the pMOS transistor 43 is connected to the interconnection 39. The source of the nMOS transistor 42 is connected to the interconnection 38. The source of the nMOS transistor 44 is connected to the interconnection 40.
In the input-output buffer region 27 adjoining the pad 30 for connection, an input-output cell 91 as shown in FIG. 11 is formed by transistors 41 to 44 shown in FIG. 10.
Referring to FIG. 11, the input-output cell 91 includes an output buffer 92 formed by the transistors 41, 42 and so on, and a diode 94. They are not connected to each other. The input-output cell 91 further includes an input buffer 93 formed by the transistors 43, 44 and so on and a diode 95. They are not connected to each other, either.
Referring to FIG. 12, in the process of personalization, if the input-output cell 91 is used as an output buffer, the output buffer 92 and a logic circuit inside of the chip are connected to each other. The output of the output buffer 92, the input of the diode 94 and the bonding pad for connection 30 are connected together. In this case, the input buffer 93 is not used. Conversely, when the input-output cell 91 is used as an input buffer, the input buffer 93 is connected to the bonding pad 30 and to the internal logic circuit.
The gate array semiconductor integrated circuit devices shown in FIGS. 9 to 12 operate as follows after being personalized. The clock signal driver 33 provides a clock signal externally applied over the clock signal input pad 32, to a subdriver 31 over the interconnection 34 with a sufficient drive capability. The subdriver 31 provides the supplied clock signal to each flipflop in the basic cell columns 28 with a sufficient drive capability. Each flipflop in the basic cell columns 28 operates as a logic circuit formed as a result of personalization.
Among the input-output cells 91 provided in connection with each bonding pad 30 for connection, ones that operate as a buffer for input supply the information externally applied through the bonding pad 30 to the flipflop of each logic circuit within the basic cell columns 28. Among the input-output cells 91, ones personalized as an output buffer supply the outputs of the flipflops of the logic circuit within the basic cell columns 28 to an external circuit through the bonding pad 30 for connection. At this time, each flipflop operates synchronizing with a clock signal applied from the clock signal input pad 32.
FIG. 13 is a plan view of a chip of another example of a conventional semiconductor integrated circuit device in which a specific method is adopted in order to control a clock skew. In FIGS. 9 and 13, the same or the corresponding portions are given the same reference designations and names. Their functions are also the same. Accordingly, a detailed description thereof will not be repeated here.
The semiconductor integrated circuit device shown in FIG. 13 is different from the device shown in FIG. 9 in that it includes, in place of the clock signal driver 33 and the subdrivers 31, a clock signal driver 46 connected to a clock signal input pad 45, and formed within the input-output buffer 27 for providing a clock signal collectively over each clock signal interconnection 47 to each flipflop in the basic cell columns 28.
The chip 26 of the semiconductor integrated circuit device shown in FIG. 13 operates as follows after the processes of personalization. A clock signal is externally applied to the clock signal driver 46 over the clock signal input pad 45. The clock signal driver 46 distributes and provides the clock signal to each flipflop through the clock signal interconnection 47 with a sufficient drive capability.
It should be noted that the clock driver 46 is formed in the region other than the power supply pin region 63 or the ground pin region 64.
The conventional semiconductor integrated circuit device, however, has disadvantages as follows. Firstly, in the case of the semiconductor integrated circuit device shown in FIG. 9, there is a possibility that the performance of each subdriver 31 varies. For that reason, it is possible that there will be a skew in a clock signal supplied from each subdriver 31. As long as the processes of the automatic layout interconnection is effected, using a CAD in the process of personalization, it is difficult to make the same the distances of interconnection between the clock signal driver 33 and each subdriver 31, and to make the same the distances between each subdriver 31 and each flipflop. Accordingly, there is a possibility that a skew due to the difference in the length of interconnection may occur in the clock signal. When each subdriver operates, there may be fluctuation in the ground potential. This fluctuation adversely affects the logic circuit as a noise.
In the semiconductor integrated circuit device shown in FIG. 13, there is a problem that the drive capability of the clock signal driver 46 must be increased as the number of gates included in the device becomes larger. For that, it is necessary to form a large clock signal driver in the input-output buffer region 27, which reduces the number of input-output buffers which may be utilized, and the number of the usable input-output pins. In accordance with Rent's law shown in FIG. 14, as the number of gates included in the gate array becomes large, the number of pins to be provided in the chip is increased. Accordingly, it is necessary to ensure as many usable pins as possible in order to increase integration of the semiconductor integrated circuit device. The use of the large clock signal driver 46 as stated above prevents the improvement in integration of a semiconductor integrated circuit device.
If the gate array is adapted for more purposes, the number of unit cells included therein becomes larger, and the number of devices used as input-output buffer is also increased. A larger area of the chip is also required for the input-output buffer. The use of a large clock signal driver prevents the gate array from being adapted to the wider range of purposes.
Furthermore, as shown in FIG. 13, when the clock signal driver and the ground pin are apart from each other, the inductance therebetween is increased. For that reason, it is possible that the noise appearing on the ground potential is increased. That is, in the case of the semiconductor integrated circuit device shown in FIG. 13, while the skew which occurs in the clock is reduced, the improvement in the performance of the semiconductor integrated circuit device is prevented.